A primary concern in fabricating complementary metal-oxide-semiconductor (CMOS) structures is the method for forming the substrates for the two types of MOS field effect transistors (MOSFETs). Early CMOS processes were developed to be compatible with the p-channel MOS (PMOS) process; hence n-channel transistors were formed in a p diffusion tub or well in the n substrate. Although some of the early processing constraints disappeared, the traditional p-well approach has remained the most widely used CMOS structure.
A p well may be implanted or diffused into an n substrate at a concentration high enough to overcompensate the n substrate and give good control over the resultant p-type doping. Typically, the doping level in the p well is five to ten times higher than that in the n-type substrate to attain this control. However, this high p-tub doping causes undesirable effects in the n-channel transistor such as increased back-gate bias effects and increased source/drain to p-well capacitance.
An alternate approach is to employ an n well to form the p-channel transistors. In this situation, the n-channel device is formed in the p-type substrate and the n-well is compatible with standard NMOS processing. However, the n well tends to overcompensate the p substrate and the p-channel devices suffer from excessive doping effects.
Another approach uses two separate wells implanted into very lightly doped n-type silicon. This "twin well" CMOS approach permits the doping profiles in each well region to be independently designed, so that neither type of device suffers from excessive doping effects. Such an approach has been used on lightly doped n-type and p-type substrates.
Briefly in a twin well CMOS process, the starting material is lightly doped n epitaxy over a heavily doped n+ substrate. If this structure is combined with proper layout techniques, CMOS circuits that are not prone to latchup are produced. Typically, after the wells are formed, isolation regions are created at the interfaces of the wells to isolate the p-channel devices from the n-channel devices. For more information on CMOS well technology, see S. M. Sze, ed. VLSI Technology, McGraw-Hill, 1983, pp. 478-485.
Shown in FIG. 1 is a CMOS structure having a lightly doped n substrate 10 within which are formed a p well 12 and an n well 14 having an n source 16 and a p source 18 respectively. The devices are isolated from each other via field oxide regions 20 and interconnection is provided by polycrystalline silicon (polysilicon) layer 22. It has been discovered with CMOS devices that when the wells are driven in, appreciable lateral diffusion occurs and interdiffusion of the wells forms a depletion region 24 under the isolation regions 20 and that if the depletion region 24 is wide enough or the substrate is too lightly doped, the depletion regions of the sources 16 and 18 and drains of adjacent transistors may punchthrough to each other and form an undesirable parasitic transistor. This effect prevents the devices from being placed close to each other and requires the use of additional chip area.
The typical solution to this problem is to form channel stop regions or "chan stops" 26 and 27 which are more highly doped regions between the active device sources 16 and 18, as seen in FIG. 2. The p-channel stop 26 and n-channel stop 27 effectively narrow the area of the depletion region 24 and permit the devices to be placed closer together. One process which employs a lift-off technique to help form combined channel stop/well regions is described by J. Y. Chen in "Quadruple-Well CMOS --A VLSI Technology," Tech. Digest, IEEE IEDM, 1982, pp. 791-792. See also U.S. Pat. No. 4,558,508 issued to Kinney, et al. on Dec. 17, 1985.
However, even with a single mask channel stop process, channel stops are often misaligned as seen in the case of misaligned channel stops 28 and 29 of FIG. 3. Because the channel stops 28 and 29 in a twin well or single well structure must be individually placed at the edge of each well, the potential for misalignment is great and the depletion region 24 is not narrowed as much as desired, causing a greater possibility of punchthrough. Using a two mask channel stop process has even greater potential for misalignment.
FIG. 4 illustrates a more typical process of forming twin well regions and an isolation oxide and channel stop between the regions. In FIG. 4A, the future n well region of the substrate 30 is receiving a phosphorus implant, represented with the Xs, through pad oxide 32 while the future p well region is shielded by nitride pattern 34. The structure in FIG. 4B is produced by driving in the phosphorus to produce n well 36, growing thick oxide layer 38 and stripping the nitride pattern 34. A boron implant is then conducted as illustrated by the dots in FIG. 4B, with n well 36 being protected by the thick oxide layer 38.
Next, the thick oxide layer 38 is stripped and a new oxide layer 40 is grown during which the p well 42 is driven in as seen in FIG. 4C. Oxide layer 40 is stripped, a new pad oxide 41 is grown and second nitride pattern 44 is formed, after which a second boron implant is conducted in the region to be the channel stop as defined by the nitride pattern 44. Photoresist pattern 46 is formed to permit the second phosphorus implant into the n well channel stop region as seen in FIG. 4D. Next, the photoresist pattern 46 is removed and the impurities are driven in slightly to form p chan stop 48 and n .chan stop 50 during or after which field oxide isolation region 52 is grown. The second nitride pattern 44 is then removed to give the structure seen in FIG. 4E.
The process described relative to FIG. 4 has a number of disadvantages, not the least of which is the fact that two mask steps are used, with their attendant risks of misalignment and the disadvantages caused by channel stop misalignment as discussed earlier. The depletion region is not as narrow as would be desired and the devices may not be placed as closely together as is desired.
An alternative process has been proposed by Hillenius and Parrillo in U.S. Pat. No. 4,554,726 (incorporated by reference herein), as illustrated in FIG. 5 which uses a single mask and permits the use of a high/low doping profile for the wells. The process begins by the future n well region of the substrate 54 receiving both an arsenic, as represented by the triangles in FIG. 5A, and a phosphorus implant, as represented by the Xs, through a blanket pad oxide 56. The future p well region is shielded by nitride pattern 58, which is the only pattern needed for the graded well formation process. By a "graded well" is meant a well with a high-low doping profile; the relatively higher doping concentration being nearer the surface.
Next, a thick oxide layer 60 is formed in the n-well region and the nitride pattern 58 is stripped. In the drive-in step for the graded n-well, which may occur during oxide layer 60 formation, the slow diffusing arsenic does not diffuse as far into the silicon with respect to the relatively fast diffusing phosphorus to give n-well 62 and highly doped surface region 64. However, since these regions 62 and 64 are driven-in simultaneously, it is difficult to achieve a shallow depth of highly doped arsenic surface region 64 if the n-well 62 is driven-in to its desired depth. As shown in FIG. 5B, the highly doped arsenic region 64 is not confined to surface proximity as would be desired. P-channel devices subsequently formed in n-well 62 perform extremely poorly.
As seen in FIG. 5B, the next step is the first boron p-well implant, as symbolized by the dots. This implant is driven-in to form p-well 66, after which a second boron implant for the highly concentrated surface region is conducted as shown in FIG. 5C. Since the drive-in of the second boron implant is performed as a separate step, the depth of highly doped boron surface region 68 may be independently determined and may be actually restricted to just below the surface unlike highly doped arsenic region 64, which must be jointly driven-in with the phosphorus. Stripping the thick oxide layer 60, forming a uniform dielectric oxide layer 70 and depositing a nitride pattern 72 produces the structure seen in FIG. 5D. Forming field oxide region 74 by high pressure oxidation or other means gives the finished isolation boundary seen in FIG. 5E. While the n-channel devices subsequently made in the p-well 66 of this structure perform well, the p-channel devices in n-well 62 suffer from excessive doping effects such as source/drain to well capacitance and body effect due to the fact that heavily doped arsenic layer 64 is too deep.
Thus, it would be desirable if a process were discovered which produced four independent well/field implants that are self-aligned, particularly if they did not require subsequent compensation implants and the depth of the heavily doped surface layers could be precisely controlled. Preferably, the channel stops produced by these implants would permit close spacing between adjacent NMOS and PMOS devices due to a low parasitic leakage, since the depletion region beneath the interface field oxide would be narrow.